A SSRW FET design is known to enhance device performance while suppressing a short-channel effect. SSRW profile refers to a low (or no) doping concentration at the surface while maintaining a high enough concentration at sub-surface region to prevent short channel problems. FIG. 1 shows super steep retrograde channel/well, for example boron (B), depth profile 101 compared to a broad channel/well doping depth profile 103. The very low doping concentration at the surface of the SSRW improves impurity scattering (therefore increasing mobility/drive current) and static random access memory (SRAM) variability (AVT). AVT is a critical parameter for SRAM Vmin determination and yield, which is associated with process variation. AVT is known to deteriorate at high doping concentrations due to random dopant fluctuations (RDF) for very small devices such as SRAM devices. Since SSRW can provide low or no doping at the surface, AVT can be significantly improved. SSRW profile can also improve short channel issues due to the very high doping profile at sub-surface regions where punch-through can happen from the drain to the source.
Attempts to form SSRW FETs have included Vt control ion implantation and a carbon doped silicon (Si:C) epitaxial barrier layer followed by silicon epitaxial layer growth. The resulting devices demonstrated 13% ion improvement and AVT improvement. However, the blanket epitaxy was grown after the shallow trench isolation (STI) chemical mechanical polishing (CMP), followed by stripping of the active region silicon nitride (SiN). In general, the field oxide height is taller than the active region after the SiN strip for further field oxide consumption during later cleaning processes, such as a pre-clean for a thick gate oxide furnace process. The step height should be close to zero before polysilicon deposition for well established technologies. Without precise control of the height between the active region and the field oxide, after the epitaxial growth, the height difference between the active region and field oxide (step height) causes process/device issues at the polysilicon gate and replacement metal gate (RMG) modules. Polysilicon gate patterning is very sensitive to substrate topology, and the final gate height varies significantly between the active regions and field oxide after polysilicon CMP at the RMG module unless the step height is close to zero.
In addition, when the field oxide surface positions lower than the active surface after epitaxial growth (a negative step height), and, therefore, the active sidewall is exposed at polysilicon deposition, a very low threshold device will be formed along the sidewall from the drain to the source, which will cause device stability issues. The step height can be controlled by etching Si using a reactive ion etch (RIE) before the epitaxy, depending on the thickness of the epitaxy, to form the flat step height. However, due to the field oxide slope which is not vertical due to the nature of the active recess process, there is always undetached Si at the bottom sidewall, resulting in residual Si where there will be unfavorable 2-dimensional (2-D) epitaxial growth rather than vertical growth. The 2-D epitaxial growth will be even more troublesome when different epitaxial layers are grown as back-to-back such as Si:C followed by a Si layer. The epitaxial layers at the bottom corner may be different from the layers at the center of the active region.
A need therefore exists for methodology enabling step height control without a silicon RIE before the epitaxial process, and the resulting devices.